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| M29W064FT M29W064FB 64 Mbit (8 Mbit x 8 or 4 Mbit x 16, page, boot block) 3 V supply Flash memory Preliminary Data Features Supply voltage - VCC = 2.7 V to 3.6 V for program, erase, read - VPP =12 V for fast program (optional) Asynchronous random/page read - Page width: 4 words - Page access: 25 ns - Random access: 60, 70 ns Programming time - 10 s per byte/word typical - 4 words/8 bytes program 135 memory blocks - 1 boot block and 7 parameter blocks, 8 Kbytes each (top or bottom location) - 127 main blocks, 64 Kbytes each Program/erase controller - Embedded byte/word program algorithms Program/erase suspend and resume - Read from any block during program suspend - Read and program another block during erase suspend Unlock Bypass Program command - Faster production/batch programming VPP/WP pin for fast program and write protect Temporary block unprotection mode Common Flash interface - 64-bit security code Device summary Root part number M29W064FT M29W064FB Device code 22EDh 22FDh TSOP48 (N) 12 x 20 mm 100,000 program/erase cycles per block Extended memory block - Extra block used as security block or to store additional information Low power consumption - Standby and automatic standby Electronic signature - Manufacturer code: 0020h Automotive device grade 3 - Temperature: -40 to 125 C - Automotive grade certified (AEC-Q100) ECOPACK(R) packages Table 1. March 2008 Rev 2 1/69 www.numonyx.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents M29W064FT, M29W064FB Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Address inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data input/output or address input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VPP/write protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset/block temporary unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ready/busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Byte/word organization select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VCC supply voltage (2.7 V to 3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 3.2 3.3 3.4 3.5 3.6 Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6.1 3.6.2 Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block protect and chip unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 4.1.2 4.1.3 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/69 M29W064FT, M29W064FB 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 Contents Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 Fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3.1 4.3.2 4.3.3 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 25 5 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 5.2 5.3 5.4 5.5 Data polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Erase timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Alternative toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 7 8 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3/69 Contents M29W064FT, M29W064FB Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Appendix C Extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 C.1 C.2 Factory locked extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Customer lockable extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Appendix D Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 D.1 D.2 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4/69 M29W064FT, M29W064FB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 28 Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Write AC characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Write AC characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Reset/block temporary unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data . . . . 43 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Top boot block addresses, M29W064FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bottom boot block addresses, M29W064FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Extended block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5/69 List of figures M29W064FT, M29W064FB List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Page read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Write AC waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Write AC waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reset/block temporary unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, top view package outline . . . . . 43 Programmer equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 In-system equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 In-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6/69 M29W064FT, M29W064FB Description 1 Description The M29W064F is a 64 Mbit (8 Mbit x 8 or 4 Mbit x 16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6 V) supply. On power-up the memory defaults to its read mode. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected in units of 256 Kbytes (generally groups of four 64 Kbyte blocks), to prevent accidental program or erase commands from modifying the memory. Program and erase commands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The device features an asymmetrical blocked architecture. The device has an array of 135 blocks: 8 parameters blocks of 8 Kbytes each (or 4 Kwords each) 127 main blocks of 64 Kbytes each (or 32 Kwords each) M29W064FT has the parameter blocks at the top of the memory address space while the M29W064FB locates the parameter blocks starting from the bottom. The M29W064F has an extra block, the extended block, of 128 words in x 16 mode or of 256 bytes in x 8 mode that can be accessed using a dedicated command. The extended block can be protected and so is useful for storing security information. However the protection is not reversible, once protected the protection cannot be undone. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The VPP/WP signal is used to enable faster programming of the device, enabling multiple word/byte programming. If this signal is held at VSS, the boot block, and its adjacent parameter block, are protected from program and erase operations. The device supports asynchronous random read and page read from all blocks of the memory array. The memories are offered in TSOP48 (12 x 20 mm) package. 7/69 Description Figure 1. Logic diagram VCC VPP/WP M29W064FT, M29W064FB 22 A0-A21 W E G RP M29W064FT M29W064FB 15 DQ0-DQ14 DQ15A-1 BYTE RB VSS AI11250b Table 2. Signal names Description Address inputs Data inputs/outputs Data inputs/outputs Direction Inputs I/O I/O I/O Input Input Input Input Output Input Supply Supply - - Name A0-A21 DQ0-DQ7 DQ8-DQ14 DQ15A-1 (or DQ15) Data input/output or address input (or data input/output) E G W RP RB BYTE VCC VPP/WP VSS NC Chip Enable Output Enable Write Enable Reset/block temporary unprotect Ready/busy output Byte/word organization select Supply voltage Supply voltage for fast program (optional) or write protect Ground Not connected internally 8/69 M29W064FT, M29W064FB Figure 2. TSOP connections A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 AI11251b Description 12 13 M29W064FT M29W064FB 37 36 24 25 9/69 Signal descriptions M29W064FT, M29W064FB 2 Signal descriptions See Figure 1: Logic diagram, and Table 2: Signal names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-A21) The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 Data inputs/outputs (DQ0-DQ7) The data I/O outputs the data stored at the selected address during a bus read operation. During bus write operations they represent the commands sent to the command interface of the program/erase controller. 2.3 Data inputs/outputs (DQ8-DQ14) The data I/O outputs the data stored at the selected address during a bus read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During bus write operations the command register does not use these bits. When reading the status register these bits should be ignored. 2.4 Data input/output or address input (DQ15A-1) When BYTE is High, VIH, this pin behaves as a data input/output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A-1 Low will select the LSB of the addressed word, DQ15A-1 High will select the MSB. Throughout the text consider references to the Data input/output to include this pin when BYTE is High and references to the address inputs to include this pin when BYTE is Low except when stated explicitly otherwise. 2.5 Chip Enable (E) The Chip Enable, E, activates the memory, allowing bus read and bus write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. 2.6 Output Enable (G) The Output Enable, G, controls the bus read operation of the memory. 10/69 M29W064FT, M29W064FB Signal descriptions 2.7 Write Enable (W) The Write Enable, W, controls the bus write operation of the memory's command interface. 2.8 VPP/write protect (VPP/WP) The VPP/write protect pin provides two functions. The VPP function allows the memory to use an external high voltage power supply to reduce the time required for unlock bypass program operations. The write protect function provides a hardware method of protecting the two outermost boot blocks. The VPP/write protect pin must not be left floating or unconnected. When VPP/write protect is Low, VIL, the memory protects the two outermost boot blocks; program and erase operations in this block are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/write protect is High, VIH, the memory reverts to the previous protection status of the two outermost boot blocks. Program and erase operations can now modify the data in the two outermost boot blocks unless the block is protected using block protection. Applying VPPH to the VPP/WP pin will temporarily unprotect any block previously protected (including the two outermost parameter blocks) using a high voltage block protection technique (in-system or programmer technique). See Table 3: Hardware protection for details. When VPP/write protect is raised to VPP the memory automatically enters the unlock bypass mode. When VPP/write protect returns to VIH or VIL normal operation resumes. During unlock bypass program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in Section 4: Command interface. The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP, see Figure 12: Accelerated program timing waveforms. Never raise VPP/Write Protect to VPP from any mode except read mode, otherwise the memory may be left in an indeterminate state. A 0.1 F capacitor should be connected between the VPP/write protect pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during unlock bypass program, IPP. Table 3. VPP/WP VIL VIH or VID VPPH Hardware protection RP VIH VID VID VIH or VID Function 2 outermost parameter blocks protected from program/erase operations All blocks temporarily unprotected except the 2 outermost blocks All blocks temporarily unprotected All blocks temporarily unprotected 11/69 Signal descriptions M29W064FT, M29W064FB 2.9 Reset/block temporary unprotect (RP) The reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. Note that if VPP/WP is at VIL, then the two outermost boot blocks will remain protected even if RP is at VID. A hardware reset is achieved by holding reset/block temporary unprotect Low, VIL, for at least tPLPX. After reset/block temporary unprotect goes High, VIH, the memory will be ready for bus read and bus write operations after tPHEL or tRHEL, whichever occurs last. See Section 2.10: Ready/busy output (RB), Table 17: Reset/block temporary unprotect AC characteristics and Figure 11: Reset/block temporary unprotect AC waveforms, for more details. Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program and erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. 2.10 Ready/busy output (RB) The ready/busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. During program or erase operations ready/busy is Low, VOL. Ready/busy is high-impedance during read mode, Auto select mode and erase suspend mode. After a hardware reset, bus read and bus write operations cannot begin until ready/busy becomes high-impedance. See Table 17: Reset/block temporary unprotect AC characteristics and Figure 11: Reset/block temporary unprotect AC waveforms, for more details. The use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. 2.11 Byte/word organization select (BYTE) The byte/word organization select pin is used to switch between the x 8 and x 16 bus modes of the memory. When byte/word organization select is Low, VIL, the memory is in x 8 mode, when it is High, VIH, the memory is in x 16 mode. 12/69 M29W064FT, M29W064FB Signal descriptions 2.12 VCC supply voltage (2.7 V to 3.6 V) VCC provides the power supply for all operations (read, program and erase). The command interface is disabled when the VCC supply voltage is less than the lockout voltage, VLKO. This prevents bus write operations from accidentally damaging the data during power-up, power-down and power surges. If the program/erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1 F capacitor should be connected between the VCC supply voltage pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. 2.13 VSS ground VSS is the reference for all voltage measurements. The device features two VSS pins which must be both connected to the system ground. 13/69 Bus operations M29W064FT, M29W064FB 3 Bus operations There are five standard bus operations that control the device. These are bus read, bus write, output disable, standby and automatic standby. See Table 4: Bus operations, BYTE = VIL and Table 5: Bus operations, BYTE = VIH, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.1 Bus read Bus read operations read from the memory cells, or specific registers in the command interface. A valid bus read operation involves setting the desired address on the address inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The data inputs/outputs will output the value, see Figure 7: Read mode AC waveforms, and Table 14: Read AC characteristics, for details of when the output becomes valid. 3.2 Bus write Bus write operations write to the command interface. To speed up the read operation the memory array can be read in page mode where data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by the address inputs A0-A1. A valid bus write operation begins by setting the desired address on the address inputs. The address inputs are latched by the command interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The data inputs/outputs are latched by the command interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole bus write operation. See Figure 9: Write AC waveforms, write enable controlled, Figure 10: Write AC waveforms, chip enable controlled, and Table 15: Write AC characteristics, write enable controlled and Table 16: Write AC characteristics, chip enable controlled, for details of the timing requirements. 3.3 Output disable The data inputs/outputs are in the high impedance state when Output Enable is High, VIH. 3.4 Standby When Chip Enable is High, VIH, the memory enters standby mode and the data inputs/outputs pins are placed in the high-impedance state. To reduce the supply current to the standby supply current, ICC2, Chip Enable should be held within VCC 0.2 V. For the standby current level see Table 13: DC characteristics. During program or erase operations the memory will continue to use the program/erase supply current, ICC3, for program or erase operations until the operation completes. 14/69 M29W064FT, M29W064FB Bus operations 3.5 Automatic standby If CMOS levels (VCC 0.2 V) are used to drive the bus and the bus is inactive for 300 ns or more the memory enters automatic standby where the internal supply current is reduced to the standby supply current, ICC2. The data inputs/outputs will still output data if a bus read operation is in progress. 3.6 Special bus operations Additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. 3.6.1 Electronic signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 4: Bus operations, BYTE = VIL and Table 5: Bus operations, BYTE = VIH. 3.6.2 Block protect and chip unprotect Groups of blocks can be protected against accidental program or erase. The protection groups are shown in Appendix A: Block addresses, Table 20 and Table 21. The whole chip can be unprotected to allow the data inside the blocks to be changed. The VPP/write protect pin can be used to protect the two outermost boot blocks. When VPP/write protect is at VIL the two outermost boot blocks are protected and remain protected regardless of the block protection status or the reset/block temporary unprotect pin status. Block protect and chip unprotect operations are described in Appendix D: Block protection. 15/69 Bus operations Table 4. Bus operations, BYTE = VIL(1) E VIL VIL X VIH VIL G VIL VIH VIH X VIL W Address inputs DQ15A-1, A0-A21 M29W064FT, M29W064FB Data inputs/outputs DQ14-DQ8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ7-DQ0 Data output Data input Hi-Z Hi-Z 20h EDh (M29W064FT) FDh (M29W064FB) 80h (factory locked) 00h (customer lockable) Operation Bus read Bus write Output disable Standby Read manufacturer code VIH Cell address VIL Command address VIH X X VIH X A0-A3 = VIL, A6 = VIL, A9 = VID, Others VIL or VIH Read device code VIL VIL A0 = VIH, A1-A3 = VIL, VIH A6 = VIL, A9 = VID, Others VIL or VIH A0 -A1 = VIH, A2-A3 = VIL, VIH A6 = VIL, A9 = VID, Others VIL or VIH A0, A2, A3, A6 = VIL, A1 = VIH, A9 = VID, VIH A12-A21 = Block address, Others VIL or VIH Hi-Z Read extended memory block verify code VIL VIL Hi-Z Read block protection status 1. X = VIL or VIH. VIL VIL Hi-Z 01h (protected) 00h (unprotected) Table 5. Bus operations, BYTE = VIH(1) E VIL VIL X VIH VIL VIL G VIL VIH VIH X VIL VIL W VIH VIL VIH X VIH VIH Address inputs A0-A21 Cell address Command address X X A0-A3 = VIL, A6 = VIL, A9 = VID, others VIL or VIH A0 = VIH, A1-A3= VIL, A6 = VIL, A9 = VID, Others VIL or VIH A0-A1 = VIH, A2-A3= VIL, A6 = VIL, A9 = VID, others VIL or VIH A0, A2, A3, A6 = VIL, A1 = VIH, A9 = VID, A12-A21 = Block address, others VIL or VIH Data inputs/outputs DQ15A-1, DQ14-DQ0 Data output Data input Hi-Z Hi-Z 0020h 22EDh (M29W064FT) 22FDh (M29W064FB) 80h (factory locked) 00h (customer lockable) Operation Bus read Bus write Output disable Standby Read manufacturer code Read device code Read extended memory block verify code VIL VIL VIH Read block protection status 1. X = VIL or VIH. VIL VIL VIH 0001h (protected) 0000h (unprotected) 16/69 M29W064FT, M29W064FB Command interface 4 Command interface All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. Failure to observe a valid sequence of bus write operations will result in the memory returning to read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 6, or Table 7, depending on the configuration that is being used, for a summary of the commands. 4.1 4.1.1 Standard commands Read/Reset command The Read/Reset command returns the memory to its read mode. It also resets the errors in the status register. Either one or three bus write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between bus write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a block erase operation then the memory will take up to 10 s to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an erase operation when issued while in erase suspend. 4.1.2 Auto Select command The Auto Select command is used to read the manufacturer code, the device code, the block protection status and the extended memory block verify code. Three consecutive bus write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in auto select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset commands are accepted in auto select mode, all other commands are ignored. In auto select mode, the manufacturer code and the device code can be read by using a bus read operation with addresses and control signals set as shown in Table 4: Bus operations, BYTE = VIL and Table 5: Bus operations, BYTE = VIH, except for A9 that is `don't care'. The block protection status of each block can be read using a bus read operation with addresses and control signals set as shown in Table 4: Bus operations, BYTE = VIL and Table 5: Bus operations, BYTE = VIH, except for A9 that is `don't care'. If the addressed block is protected then 01h is output on data inputs/outputs DQ0-DQ7, otherwise 00h is output (in 8-bit mode). The protection status of the extended memory block, or extended memory block verify code, can be read using a bus read operation with addresses and control signals set as shown in Table 4: Bus operations, BYTE = VIL and Table 5: Bus operations, BYTE = VIH, except for A9 that is `don't care'. If the extended block is factory locked then 80h is output on data input/outputs DQ0-DQ7, otherwise 00h is output (8-bit mode). 17/69 Command interface M29W064FT, M29W064FB 4.1.3 Read CFI Query command The Read CFI Query command is used to read data from the common Flash interface (CFI) memory area. This command is valid when the device is in the read array mode, or when the device is in auto selected mode. One bus write cycle is required to issue the Read CFI Query command. Once the command is issued subsequent bus read operations read from the common Flash Interface memory area. The Read/Reset command must be issued to return the device to the previous mode (the read array mode or autoselected mode). A second Read/Reset command would be needed if the device is to be put in the read array mode from autoselected mode. See Appendix B: Common Flash interface (CFI), Tables 22, 23, 24, 25, 26 and 27 for details on the information contained in the common Flash interface (CFI) memory area. 4.1.4 Chip Erase command The Chip Erase command can be used to erase the entire chip. Six bus write operations are required to issue the Chip Erase command and start the program/erase controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the chip erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 8: Program, erase times and program, erase endurance cycles. All bus read operations during the chip erase operation will output the status register on the data inputs/outputs. See the section on the status register for more details. After the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. When an error occurs the memory will continue to output the status register. A Read/Reset command must be issued to reset the error condition and return to read mode. The Chip Erase command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost. 18/69 M29W064FT, M29W064FB Command interface 4.1.5 Block Erase command The Block Erase command can be used to erase a list of one or more blocks. Six bus write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. The block erase operation starts the program/erase controller about 50 s after the last bus write operation. Once the program/erase controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50 s of the last block. The 50 s timer restarts when an additional block is selected. The status register can be read after the sixth bus write operation. See the status register section for details on how to identify if the program/erase controller has started the block erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the block erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 8: Program, erase times and program, erase endurance cycles. All bus read operations during the block erase operation will output the status register on the data inputs/outputs. See the section on the status register for more details. After the block erase operation has completed the memory will return to the read mode, unless an error has occurred. When an error occurs the memory will continue to output the status register. A Read/Reset command must be issued to reset the error condition and return to read mode. The Block Erase command sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost. 4.1.6 Erase Suspend command The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to read mode. The command requires one bus write operation. The program/erase controller will suspend within the erase suspend latency time of the Erase Suspend command being issued. Once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start immediately when the Erase Resume command is issued. It is not possible to select any further blocks to erase after the erase resume. During erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The status register is not read and no error condition is given. Reading from blocks that are being erased will output the status register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an erase suspend. The Read/Reset command must be issued to return the device to read array mode before the Resume command will be accepted. 19/69 Command interface M29W064FT, M29W064FB 4.1.7 Erase Resume command The Erase Resume command must be used to restart the program/erase controller after an erase suspend. The device must be in read array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once. 4.1.8 Program Suspend command The Program Suspend command allows the system to interrupt a program operation so that data can be read from any block. When the Program Suspend command is issued during a program operation, the device suspends the program operation within the program suspend latency time (see Table 8: Program, erase times and program, erase endurance cycles for value) and updates the status register bits. After the program operation has been suspended, the system can read array data from any address. However, data read from program-suspended addresses is not valid. The Program Suspend command may also be issued during a program operation while an erase is suspended. In this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the extended block area (one-time program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the Auto Select command sequence when the device is in the program suspend mode. The system can read as many auto select codes as required. When the device exits the auto select mode, the device reverts to the program suspend mode, and is ready for another valid operation. See Auto Select command sequence for more information. 4.1.9 Program Resume command After the Program Resume command is issued, the device reverts to programming. The controller can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See write operation status for more information. The system must write the Program Resume command, to exit the program suspend mode and to continue the programming operation. Further issuing of the Resume command is ignored. Another Program Suspend command can be written after the device has resumed programming. 20/69 M29W064FT, M29W064FB Command interface 4.1.10 Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four bus write operations, the final write operation latches the address and data, and starts the program/erase controller. Programming can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 4.1.8: Program Suspend command and Section 4.1.9: Program Resume command). If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The status register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 8: Program, erase times and program, erase endurance cycles. Bus read operations during the program operation will output the status register on the data inputs/outputs. See the section on the status register for more details. After the program operation has completed the memory will return to the read mode, unless an error has occurred. When an error occurs the memory will continue to output the status register. A Read/Reset command must be issued to reset the error condition and return to read mode. Note that the Program command cannot change a bit set to '0' back to '1'. One of the erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. 21/69 Command interface M29W064FT, M29W064FB 4.2 Fast program commands There are four fast program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel. The Double, Quadruple and Octuple Byte Program commands are available for x 8 operations, while the Double, Quadruple Word Program commands are available for x 16 operations. Fast program commands can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 4.1.8: Program Suspend command and Section 4.1.9: Program Resume command). When VPPH is applied to the VPP/write protect pin the memory automatically enters the fast program mode. The user can then choose to issue any of the fast program commands. Care must be taken because applying a VPPH to the VPP/WP pin will temporarily unprotect any protected block. 4.2.1 Double Byte Program command The Double Byte Program command is used to write a page of two adjacent bytes in parallel. The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to issue the Double Byte Program command. 1. 2. 3. The first bus cycle sets up the Double Byte Program command The second bus cycle latches the address and the data of the first byte to be written The third bus cycle latches the address and the data of the second byte to be written. 4.2.2 Quadruple Byte Program command The Quadruple Byte Program command is used to write a page of four adjacent bytes in parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are necessary to issue the Quadruple Byte Program command. 1. 2. 3. 4. 5. The first bus cycle sets up the Quadruple Byte Program command The second bus cycle latches the Address and the data of the first byte to be written The third bus cycle latches the address and the data of the second byte to be written The fourth bus cycle latches the address and the data of the third byte to be written The fifth bus cycle latches the address and the data of the fourth byte to be written and starts the program/erase controller. 22/69 M29W064FT, M29W064FB Command interface 4.2.3 Octuple Byte Program command This is used to write eight adjacent bytes, in x 8 mode, simultaneously. The addresses of the eight bytes must differ only in A1, A0 and DQ15A-1. Nine bus write cycles are necessary to issue the command: 1. 2. 3. 4. 5. 6. 7. 8. 9. The first bus cycle sets up the command The second bus cycle latches the address and the data of the first byte to be written The third bus cycle latches the address and the data of the second byte to be written The fourth bus cycle latches the address and the data of the third byte to be written The fifth bus cycle latches the address and the data of the fourth byte to be written The sixth bus cycle latches the address and the data of the fifth byte to be written The seventh bus cycle latches the address and the data of the sixth byte to be written The eighth bus cycle latches the address and the data of the seventh byte to be written. The ninth bus cycle latches the address and the data of the eighth byte to be written and starts the program/erase controller. 4.2.4 Double Word Program command The Double Word Program command is used to write a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus write cycles are necessary to issue the Double Word Program command: The first bus cycle sets up the Quadruple Word Program command. The second bus cycle latches the address and the data of the first word to be written The third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. After the program operation has completed the memory will return to the read mode, unless an error has occurred. When an error occurs bus read operations will continue to output the status register. A Read/Reset command must be issued to reset the error condition and return to read mode. Note that the fast program commands cannot change a bit set to '0' back to '1'. One of the erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Typical program times are given in Table 8: Program, erase times and program, erase endurance cycles. 23/69 Command interface M29W064FT, M29W064FB 4.2.5 Quadruple Word Program command This is used to write a page of four adjacent words (or 8 adjacent bytes), in x 16 mode, simultaneously. The addresses of the four words must differ only in A1 and A0. Five bus write cycles are necessary to issue the command: The first bus cycle sets up the command The second bus cycle latches the address and the data of the first word to be written The third bus cycle latches the address and the data of the second word to be written The fourth bus cycle latches the address and the data of the third word to be written The fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. 4.2.6 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three bus write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in read mode. When VPP is applied to the VPP/write protect pin the memory automatically enters the unlock bypass mode and the Unlock Bypass Program command can be issued immediately. 4.2.7 Unlock Bypass Program command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three bus write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in read mode. The memory offers accelerated program operations through the VPP/write protect pin. When the system asserts VPP on the VPP/write protect pin, the memory automatically enters the unlock bypass mode. The system may then write the two-cycle unlock bypass program command sequence. The memory uses the higher voltage on the VPP/write protect pin, to accelerate the unlock bypass program operation. Never raise VPP/write protect to VPP from any mode except read mode, otherwise the memory may be left in an indeterminate state. 4.2.8 Unlock Bypass Reset command The Unlock Bypass Reset command can be used to return to read/reset mode from Unlock bypass mode. Two bus write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from unlock bypass mode. 24/69 M29W064FT, M29W064FB Command interface 4.3 4.3.1 Block Protection commands Enter Extended Block command The device has an extra 256-byte block (extended block) that can only be accessed using the Enter Extended Block command. Three bus write cycles are required to issue the Extended Block command. Once the command has been issued the device enters extended block mode where all bus read or write operations to the boot block addresses access the extended block. The extended block (with the same address as the boot blocks) cannot be erased, and can be treated as one-time programmable (OTP) memory. In extended block mode the boot blocks are not accessible. To exit from the extended block mode the Exit Extended Block command must be issued. The extended block can be protected, however once protected the protection cannot be undone. 4.3.2 Exit Extended Block command The Exit Extended Block command is used to exit from the extended block mode and return the device to read mode. Four bus write operations are required to issue the command. 4.3.3 Block Protect and Chip Unprotect commands Groups of blocks can be protected against accidental program or erase. The Protection groups are shown in Appendix A: Block addresses, Table 20: Top boot block addresses, M29W064FT and Table 21: Bottom boot block addresses, M29W064FB. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block protect and chip unprotect operations are described in Appendix D: Block protection. 25/69 Command interface Table 6. Commands, 16-bit mode, BYTE = VIH(1) Bus write operations Length Command 1st 2nd 3rd Addr 4th M29W064FT, M29W064FB 5th 6th Addr Data Addr Data 1 Read/Reset 3 Auto Select Program Double Word Program Quadruple Word Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Program/Erase Suspend Program/Erase Resume Read CFI Query Enter Extended Block Exit Extended Block 3 4 3 5 3 2 2 6 6+ 1 1 1 3 4 555 555 555 555 555 555 X X 555 555 X X 55 555 555 AA AA AA 50 56 AA A0 90 AA AA B0 30 98 AA AA 2AA 2AA 55 55 2AA 2AA 2AA PA0 PA0 2AA PA X 2AA 2AA 55 55 55 PD0 PD0 55 PD 00 55 55 X F0 Data Addr Data Addr Data Addr Data X 555 555 PA1 PA1 555 F0 90 A0 PD1 PD1 20 PA2 PD2 PA3 PD3 PA PD 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 BA 10 30 555 555 88 90 X 00 1. X don't care, PA program address, PD program data, BA any address in the block. All values in the table are in hexadecimal. The command interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are don't care. DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH. 26/69 M29W064FT, M29W064FB Table 7. Command Command interface Commands, 8-bit mode, BYTE = VIL Length Bus write operations(1) 1st 2nd 3rd 4th 5th 6th 7th 8th 9th Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data X F0 X F0 PA PD Read/Reset Auto Select Program Double Byte Program Quadruple Byte Program Octuple Byte Program 1 3 AAA AA 555 55 3 AAA AA 555 55 AAA 90 4 AAA AA 555 55 AAA A0 3 AAA 50 PA0 PD0 PA1 PD1 5 AAA 56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 9 AAA 8B PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass 2 Program Unlock Bypass 2 Reset Chip Erase Block Erase X X A0 90 PA X PD 00 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 X X AA B0 30 98 BA 30 Program/Erase 1 Suspend Program/Erase 1 Resume Read CFI Query Enter Extended Block Exit Extended Block 1 3 AAA AA 555 55 AAA 88 4 AAA AA 555 55 AAA 90 X 00 1. X don't care, PA program address, PD program data, BA any address in the block. All values in the table are in hexadecimal. The command interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are don't care. DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH. 27/69 Command interface Table 8. M29W064FT, M29W064FB Program, erase times and program, erase endurance cycles Parameter Min Typ(1)(2) 80 0.8 Max(2) 400(3) 6 (4) (4) Unit s s s s s s s s s s s s cycles years Chip Erase Block Erase (64 Kbytes) Erase Suspend latency time Program (byte or word) Double Byte Double Word /Quadruple Byte Program Quadruple Word / Octuple Byte Program Chip Program (byte by byte) Chip Program (word by word) Chip Program (Double Word/Quadruple Byte Program) Chip Program (Quadruple Word/Octuple Byte Program) Program Suspend latency time Program/Erase cycles (per block) Data retention 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. 50 10 10 10 10 80 40 20 10 200(3) 200 (3) (3) 200 200(3) 400(3) 200 (3) 100(3) 50 (3) 4 100,000 20 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and VCC. 28/69 M29W064FT, M29W064FB Status register 5 Status register Bus read operations from any address always read the status register during program and erase operations. It is also read during erase suspend when an address within a block being erased is accessed. The bits in the status register are summarized in Table 9: Status register bits. 5.1 Data polling bit (DQ7) The data polling bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. The data polling bit is output on DQ7 when the status register is read. During program operations the data polling bit outputs the complement of the bit being programmed to DQ7. After successful completion of the program operation the memory returns to read mode and bus read operations from the address just programmed output DQ7, not its complement. During erase operations the data polling bit outputs '0', the complement of the erased state of DQ7. After successful completion of the erase operation the memory returns to read mode. In erase suspend mode the data polling bit will output a '1' during a bus read operation within a block being erased. The data polling bit will change from a '0' to a '1' when the program/erase controller has suspended the erase operation. Figure 3: Data polling flowchart, gives an example of how to use the data polling bit. A valid address is the address being programmed or an address within the block being erased. 5.2 Toggle bit (DQ6) The toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. The toggle bit is output on DQ6 when the status register is read. During program and erase operations the toggle bit changes from '0' to '1' to '0', etc., with successive bus read operations at any address. After successful completion of the operation the memory returns to read mode. During erase suspend mode the toggle bit will output when addressing a cell within a block being erased. The toggle bit will stop toggling when the program/erase controller has suspended the erase operation. Figure 4: Toggle flowchart, gives an example of how to use the toggle bit. 29/69 Status register M29W064FT, M29W064FB 5.3 Error bit (DQ5) The error bit can be used to identify errors detected by the program/erase controller. The error bit is set to '1' when a program, block erase or chip erase operation fails to write the correct data to the memory. If the error bit is set a Read/Reset command must be issued before other commands are issued. The error bit is output on DQ5 when the status register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A bus read operation to that address will show the bit is still `0'. One of the erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. 5.4 Erase timer bit (DQ3) The erase timer bit can be used to identify the start of program/erase controller operation during a Block Erase command. Once the program/erase controller starts erasing the erase timer bit is set to '1'. Before the program/erase controller starts the erase timer bit is set to '0' and additional blocks to be erased may be written to the command interface. The erase timer bit is output on DQ3 when the status register is read. 5.5 Alternative toggle bit (DQ2) The alternative toggle bit can be used to monitor the program/erase controller during erase operations. The alternative toggle bit is output on DQ2 when the status register is read. During chip erase and block erase operations the toggle bit changes from '0' to '1' to '0', etc., with successive bus read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to read mode. During erase suspend the alternative toggle bit changes from '0' to '1' to '0', etc. with successive bus read operations from addresses within the blocks being erased. Bus read operations to addresses within blocks not being erased will output the memory cell data as if in read mode. After an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the error. The alternative toggle bit changes from '0' to '1' to '0', etc. with successive bus read operations from addresses within blocks that have not erased correctly. The alternative toggle bit does not change if the addressed block has erased correctly. 30/69 M29W064FT, M29W064FB Table 9. Status register bits(1) Address Any address Any address Any address Any address Erasing block Non-erasing block Erasing block Block erase Non-erasing block Erasing block Erase suspend Non-erasing block Good block address Erase error Faulty block address 1. Unspecified data bits should be ignored. Status register Operation Program Program during erase suspend Program error Chip erase Block erase before timeout DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1 DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle DQ5 0 0 1 0 0 0 0 0 0 DQ3 - - - 1 0 0 1 1 - DQ2 - - - Toggle Toggle No Toggle Toggle No Toggle Toggle RB 0 0 Hi-Z 0 0 0 0 0 Hi-Z Hi-Z Data read as normal 0 0 Toggle Toggle 1 1 1 1 No Toggle Hi-Z Toggle Hi-Z Figure 3. Data polling flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO YES DQ5 =1 YES READ DQ7 at VALID ADDRESS DQ7 = DATA NO FAIL YES PASS AI90194 31/69 Status register Figure 4. Toggle flowchart START READ DQ6 M29W064FT, M29W064FB READ DQ5 & DQ6 DQ6 = TOGGLE YES NO NO DQ5 =1 YES READ DQ6 TWICE DQ6 = TOGGLE YES FAIL NO PASS AI90195B 32/69 M29W064FT, M29W064FB Maximum rating 6 Maximum rating Stressing the device above the rating listed in Table 10: Absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 10. Symbol TBIAS TSTG VIO VCC VID VPP(3) Absolute maximum ratings Parameter Temperature under bias Storage temperature Input or output Supply voltage Identification voltage Program voltage voltage(1)(2) Min -50 -65 -0.6 -0.6 -0.6 -0.6 Max 125 150 VCC + 0.6 4 13.5 13.5 Unit C C V V V V 1. Minimum voltage may undershoot to -2 V during transition and for less than 20 ns during transitions. 2. Maximum voltage may overshoot to VCC +2 V during transition and for less than 20 ns during transitions. 3. VPP must not remain at 12 V for more than a total of 80 hrs. 33/69 DC and AC parameters M29W064FT, M29W064FB 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 11. Operating and AC measurement conditions M29W064FT, M29W064FB Parameter Min VCC supply voltage Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages 0 to VCC VCC/2 2.7 -40 30 10 Max 3.6 85 V C pF ns V V Unit Figure 5. AC measurement I/O waveform VCC VCC/2 0V AI05557 Figure 6. AC measurement load circuit VPP VCC VCC 25k DEVICE UNDER TEST 25k CL 0.1F 0.1F CL includes JIG capacitance AI05558 34/69 M29W064FT, M29W064FB Table 12. Symbol CIN COUT DC and AC parameters Device capacitance Parameter Input capacitance Output capacitance Test condition VIN = 0 V VOUT = 0 V Min Max 6 12 Unit pF pF 1. Sampled only, not 100% tested. Table 13. Symbol ILI ILO ICC1 ICC2 DC characteristics Parameter Input leakage current Output leakage current Supply current (read) Supply current (standby) Test condition 0 V VIN VCC 0 V VOUT VCC E = VIL, G = VIH, f = 6 MHz E = VCC 0.2 V, RP = VCC 0.2 V Program/erase controller active VPP/WP = VIL or VIH VPP/WP = VPP Min Max 1 1 10 100 20 20 -0.5 0.7VCC VCC = 2.7 V 10% VCC = 2.7 V 10% IOL = 1.8 mA IOH = -100 A VCC-0.4 11.5 1.8 12.5 2.3 11.5 0.8 VCC + 0.3 12.5 15 0.45 Unit A A mA A ICC3 VIL VIH VPP IPP VOL VOH VID VLKO(1) Supply current (program/erase) Input low voltage Input high voltage Voltage for VPP/WP program acceleration Current for VPP/WP program acceleration Output low voltage Output high voltage Identification voltage Program/erase lockout supply voltage mA mA V V V mA V V V V 1. Sampled only, not 100% tested. 35/69 DC and AC parameters Figure 7. Read mode AC waveforms M29W064FT, M29W064FB tAVAV A0-A20/ A-1 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7/ DQ8-DQ15 tBHQV BYTE tELBL/tELBH tBLQZ AI05559 VALID tAXQX tEHQX tEHQZ tGHQX tGHQZ VALID Figure 8. Page read AC waveforms A2-A21 VALID ADDRESS A0-A1 VALID tAVQV VALID VALID VALID E tELQV tEHQX tEHQZ G tGHQX tGLQV DQ0-DQ15 VALID DATA tAVQV1 VALID DATA VALID DATA tGHQZ VALID DATA AI11553 36/69 M29W064FT, M29W064FB Table 14. Symbol DC and AC parameters Read AC characteristics Alt Parameter Test condition M29W064FT, M29W064FB 60 70 70 70 25 0 70 0 25 25 25 0 ns ns ns ns ns ns ns ns ns ns Unit tAVAV tAVQV tAVQV1 tELQX(1) tELQV tGLQX(1) tGLQV tEHQZ(1) tGHQZ(1) tEHQX tGHQX tAXQX tELBL tELBH tBLQZ tBHQV tRC tACC Address Valid to Next Address Valid Address Valid to Output Valid E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Min Max Max Min Max Min Max Max Max Min 60 60 25 0 60 0 25 25 25 0 tPAGE Address Valid to Output Valid (Page) tLZ tCE tOLZ tOE tHZ tDF tOH tELFL tELFH tFLQZ Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition Chip Enable to BYTE Low or High BYTE Low to Output Hi-Z Max Max Max 5 25 30 5 25 30 ns ns ns tFHQV BYTE High to Output Valid 1. Sampled only, not 100% tested. 37/69 DC and AC parameters Figure 9. Write AC waveforms, write enable controlled M29W064FT, M29W064FB tAVAV A0-A20/ A-1 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX tWLWH tWHGL tWHEH VCC tVCHEL RB tWHRL AI05560 38/69 M29W064FT, M29W064FB Table 15. Symbol DC and AC parameters Write AC characteristics, write enable controlled Alt Parameter M29W064FT, M29W064FB 60 70 70 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL(1) tVCHEL tWC tCS tWP tDS tDH tCH tWPH tAS tAH Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 60 0 45 45 0 0 30 0 45 0 0 30 50 tOEH tBUSY tVCS Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low 1. Sampled only, not 100% tested. 39/69 DC and AC parameters Figure 10. Write AC waveforms, chip enable controlled tAVAV A0-A20/ A-1 VALID tELAX tAVEL W tWLEL G tGHEL E tELEH M29W064FT, M29W064FB tEHWH tEHGL tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX VCC tVCHWL RB tEHRL AI05561 40/69 M29W064FT, M29W064FB Table 16. Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tEHRL(1) tVCHWL tOEH DC and AC parameters Write AC characteristics, chip enable controlled M29W064FT, M29W064FB Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 60 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low Chip Enable High to Output Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 60 0 45 45 0 0 30 0 45 0 0 30 50 70 70 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit tBUSY Program/Erase Valid to RB Low tVCS VCC High to Write Enable Low 1. Sampled only, not 100% tested. Figure 11. Reset/block temporary unprotect AC waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH AI02931B 41/69 DC and AC parameters Figure 12. Accelerated program timing waveforms M29W064FT, M29W064FB VPP VPP/WP VIL or VIH tVHVPP tVHVPP AI05563 Table 17. Symbol tPHWL(1) tPHEL tPHGL(1) tRHWL(1) tRHEL(1) tRHGL(1) tPLPX tPLYH tPHPHH(1) tVHVPP(1) Reset/block temporary unprotect AC characteristics Alt Parameter M29W064FT, M29W064FB Unit tRH RP High to Write Enable Low, Chip Enable Low, Output Enable Low Min 50 ns tRB tRP tREADY tVIDR RB High to Write Enable Low, Chip Enable Low, Output Enable Low RP pulse width RP Low to read mode RP rise time to VID VPP rise and fall time Min Min Max Min Min 0 500 50 500 250 ns ns s ns ns 1. Sampled only, not 100% tested. 42/69 M29W064FT, M29W064FB Package mechanical 8 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. ECOPACK packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 13. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, top view package outline 1 48 e D1 B 24 25 L1 A2 A E1 E DIE A1 C CP L TSOP-G 1. Drawing is not to scale. Table 18. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data millimeters inches Max 1.20 0.10 1.00 0.22 0.05 0.95 0.17 0.10 0.15 1.05 0.27 0.21 0.10 12.00 20.00 18.40 0.50 0.60 0.80 3 0 5 11.90 19.80 18.30 - 0.50 12.10 20.20 18.50 - 0.70 0.472 0.787 0.724 0.020 0.024 0.031 3 0 5 0.468 0.779 0.720 - 0.020 0.004 0.039 0.009 0.002 0.037 0.007 0.004 Typ Min Max 0.047 0.006 0.041 0.011 0.008 0.004 0.476 0.795 0.728 - 0.028 Symbol Typ A A1 A2 B C CP D1 E E1 e L L1 Min 43/69 Ordering information M29W064FT, M29W064FB 9 Ordering information Table 19. Example: Device type M29 Operating voltage W = VCC = 2.7 to 3.6 V Device function 064F = 64 Mbit (x 8 / x 16), boot block Array matrix T = Top boot B = Bottom boot Speed 60 = 60 ns 70 = 70 ns Package N = TSOP48: 12 x 20 mm Temperature range 40 3 = automotive grade certified(1), - to 125 C Option E = ECOPACK package, standard packing F = ECOPACK package, tape & reel packing Ordering information scheme M29W064FB 70 N 3 F 1. Qualified and characterized according to AEC Q100 & Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. Note: This product is also available with the extended block factory locked. For further details and ordering information contact your nearest Numonyx sales office. Devices are shipped from the factory with the memory content bits erased to `1'. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx sales office. 44/69 M29W064FT, M29W064FB Block addresses Appendix A Table 20. Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Block addresses Top boot block addresses, M29W064FT Kbytes/Kwords 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 1E0000h-1EFFFFh 1F0000h-1FFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh Protection block group (x 8) 000000h-00FFFFh(1) 010000h-01FFFFh (x 16) 000000h-007FFFh(1) 008000h-00FFFFh 45/69 Block addresses Table 20. Block 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 M29W064FT, M29W064FB Top boot block addresses, M29W064FT (continued) Kbytes/Kwords 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 3E0000h-3EFFFFh 3F0000h-3FFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh Protection block group (x 8) 200000h-20FFFFh 210000h-21FFFFh (x 16) 100000h-107FFFh 108000h-10FFFFh 46/69 M29W064FT, M29W064FB Table 20. Block 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Block addresses Top boot block addresses, M29W064FT (continued) Kbytes/Kwords 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 5E0000h-5EFFFFh 5F0000h-5FFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh Protection block group (x 8) 400000h-40FFFFh 410000h-41FFFFh (x 16) 200000h-207FFFh 208000h-20FFFFh 47/69 Block addresses Table 20. Block 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 M29W064FT, M29W064FB Top boot block addresses, M29W064FT (continued) Kbytes/Kwords 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 7A0000h-7AFFFFh 7B0000h-7BFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh Protection block group (x 8) 600000h-60FFFFh 610000h-61FFFFh (x 16) 300000h-307FFFh 308000h-30FFFFh 48/69 M29W064FT, M29W064FB Table 20. Block 124 125 126 127 128 129 130 131 132 133 134 Block addresses Top boot block addresses, M29W064FT (continued) Kbytes/Kwords 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 Protection group Protection block group (x 8) 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7F1FFFh 7F2000h-7F3FFFh 7F4000h-7F5FFFh 7F6000h-7F7FFFh 7F8000h-7F9FFFh 7FA000h-7FBFFFh 7FC000h-7FDFFFh 7FE000h-7FFFFFh (x 16) 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh 1. Used as the extended block addresses in extended block mode. 49/69 Block addresses Table 21. Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 M29W064FT, M29W064FB Bottom boot block addresses, M29W064FB Kbytes/Kwords 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 1A0000h-1AFFFFh 1B0000h-1BFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh Protection group Protection block group (x 8) 000000h-001FFFh(1) 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh (x 16) 000000h-000FFFh(1) 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 50/69 M29W064FT, M29W064FB Table 21. Block 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Block addresses Bottom boot block addresses, M29W064FB (continued) Kbytes/Kwords 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 3A0000h-3AFFFFh 3B0000h-3BFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh Protection block group (x 8) 1C0000h-1CFFFFh 1D0000h-1DFFFFh (x 16) 0E0000h-0E7FFFh 0E8000h-0EFFFFh 51/69 Block addresses Table 21. Block 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 M29W064FT, M29W064FB Bottom boot block addresses, M29W064FB (continued) Kbytes/Kwords 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 5A0000h-5AFFFFh 5B0000h-5BFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh Protection block group (x 8) 3C0000h-3CFFFFh 3D0000h-3DFFFFh (x 16) 1E0000h-1E7FFFh 1E8000h-1EFFFFh 52/69 M29W064FT, M29W064FB Table 21. Block 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Block addresses Bottom boot block addresses, M29W064FB (continued) Kbytes/Kwords 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 64/32 64/32 Protection group 64/32 64/32 7A0000h-7AFFFFh 7B0000h-7BFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh Protection block group (x 8) 5C0000h-5CFFFFh 5D0000h-5DFFFFh (x 16) 2E0000h-2E7FFFh 2E8000h-2EFFFFh 53/69 Block addresses Table 21. Block 131 132 133 134 M29W064FT, M29W064FB Bottom boot block addresses, M29W064FB (continued) Kbytes/Kwords 64/32 64/32 Protection group 64/32 64/32 7E0000h-7EFFFFh 7F0000h-7FFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh Protection block group (x 8) 7C0000h-7CFFFFh 7D0000h-7DFFFFh (x 16) 3E0000h-3E7FFFh 3E8000h-3EFFFFh 1. Used as the extended block addresses in extended block mode. 54/69 M29W064FT, M29W064FB Common Flash interface (CFI) Appendix B Common Flash interface (CFI) The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query command is issued the device enters CFI query mode and the data structure is read from the memory. Tables 22, 23, 24, 25, 26, and 27, show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64-bit unique security number is written (see Table 27: Security code area). This area can be accessed only in read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Table 22. Address Sub-section name x 16 10h 1Bh 27h 40h 61h x8 20h 36h 4Eh 80h C2h CFI query identification string System interface information Device geometry definition Primary algorithm-specific extended query table Security code area Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the primary algorithm (optional) 64-bit unique device number Description Query structure overview(1) 1. Query data are always presented on the lowest order data outputs. 55/69 Common Flash interface (CFI) Table 23. Address Data x 16 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah x8 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 0051h 0052h Query unique ASCII string `QRY' 0059h Description M29W064FT, M29W064FB CFI query identification string(1) Value `Q' `R' `Y' AMD compatible P = 40h 0002h Primary algorithm command set and control interface ID code 0000h 16-bit ID code defining a specific algorithm 0040h Address for primary algorithm extended query table (see 0000h Table 26) 0000h Alternate vendor command set and control interface ID code 0000h second vendor - specified algorithm supported 0000h Address for alternate algorithm extended query table 0000h NA NA 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'. Table 24. Address CFI query system interface information Data Description Value x 16 x8 VCC logic supply minimum program/erase voltage 0027h bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VCC logic supply maximum program/erase voltage 0036h bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VPP [programming] supply minimum program/erase voltage 00B5h bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV 1Bh 36h 2.7 V 1Ch 38h 3.6 V 1Dh 3Ah 11.5 V VPP [programming] supply maximum program/erase voltage 1Eh 3Ch 00C5h bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV 1Fh 20h 21h 22h 23h 24h 25h 26h 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 0004h Typical timeout per single byte/word program = 2n s 0000h Typical timeout for minimum size write buffer program = 2 s 000Ah Typical timeout per individual block erase = 2 ms 0000h Typical timeout for full chip erase = 2 ms 0004h Maximum timeout for byte/word program = 2n times typical 0000h Maximum timeout for write buffer program = 2n times typical 0003h Maximum timeout per individual block erase = 2 times typical 0000h Maximum timeout for chip erase = 2 times typical n n n n n 12.5 V 16 s NA 1s NA 256 s NA 8s NA 56/69 M29W064FT, M29W064FB Table 25. Address Data x 16 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch x8 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 0017h Device size = 2n in number of bytes Description Common Flash interface (CFI) Device geometry definition(1) Value 8 Mbytes x 8, x 16 Async. 16 bytes 2 8 8 Kbytes 127 64 Kbytes 0002h Flash device interface code description 0000h 0004h Maximum number of bytes in multi-byte program or page = 2n 0000h 0002h Number of erase block regions. It specifies the number of regions containing contiguous erase blocks of the same size. 0007h Region 1 information 0000h Number of erase blocks of identical size = 0007h+1 0020h Region 1 information 0000h Block size in region 1 = 0020h * 256 byte 007Eh Region 2 information 0000h Number of erase blocks of identical size= 007Eh+1 0000h Region 2 information 0001h Block size in region 2 = 0100h * 256 byte 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Region 3 information Number of erase blocks of identical size=007Fh+1 Region 3 information Block size in region 3 = 0000h * 256 bytes Region 4 information Number of erase blocks of identical size=007Fh+1 Region 4 information Block size in region 4 = 0000h * 256 bytes 0 0 0 0 1. For bottom boot devices, erase block region 1 is located from address 000000h to 007FFFh and erase block region 2 from address 008000h to 3FFFFFh. For top boot devices, erase block region 1 is located from address 000000h to 3F7FFFh and erase block region 2 from address 3F8000h to 3FFFFFh. 57/69 Common Flash interface (CFI) Table 26. Address Data x 16 40h 41h 42h 43h 44h 45h x8 80h 82h 84h 86h 88h 8Ah 0050h Description M29W064FT, M29W064FB Primary algorithm-specific extended query table Value `P' `R' `I' `1' `3' Yes Primary algorithm extended query table unique ASCII string 0052h `PRI' 0049h 0031h Major version number, ASCII 0033h Minor version number, ASCII Address sensitive unlock (bits 1 to 0) 0000h 00h = required, 01h = not required Silicon revision number (bits 7 to 2) 0002h 0004h 0001h 0004h Erase suspend 00h = not supported, 01h = read only, 02 = read and write Block protection 00h = not supported, x = number of blocks per protection group Temporary block unprotect 00h = not supported, 01h = supported Block protect /unprotect 04 = M29W064F 46h 47h 48h 49h 4Ah 4Bh 4Ch 8Ch 8Eh 90h 92h 94h 96h 98h 2 4 Yes 04 No No Yes 0000h Simultaneous operations, 00h = not supported 0000h Burst mode: 00h = not supported, 01h = supported 0001h Page mode: 00h = not supported, 01h = 4 page word, 02h = 8 page word 4Dh 9Ah VPP supply minimum program/erase voltage 00B5h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP supply maximum program/erase voltage 00C5h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Top/bottom boot block flag 0002h 02h = bottom boot device 0003h 03h = top boot device Program suspend 0001h 00h = not supported 01h = supported 11.5 V 4Eh 9Ch 12.5 V 4Fh 9Eh - 50h A0h Supported 58/69 M29W064FT, M29W064FB Table 27. Security code area Data x 16 61h 62h 63h 64h x8 C3h, C2h C5h, C4h C7h, C6h C9h, C8h XXXX XXXX Common Flash interface (CFI) Address Description 64 bit: unique device number XXXX XXXX 59/69 Extended memory block M29W064FT, M29W064FB Appendix C Extended memory block The M29W064F has an extra block, the extended block, that can be accessed using a dedicated command. This extended block is 128 words in x 16 mode and 256 bytes in x 8 mode. It is used as a security block to provide a permanent security identification number) or to store additional information. The extended block is either factory locked or customer lockable, its status is indicated by bit DQ7. This bit is permanently set to either `1' or `0' at the factory and cannot be changed. When set to `1', it indicates that the device is factory locked and the extended block is protected. When set to `0', it indicates that the device is customer lockable and the extended block is unprotected. Bit DQ7 being permanently locked to either `1' or `0' is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bit DQ7 is the most significant bit in the extended block verify code and a specific procedure must be followed to read it. See `extended memory block verify code' in Table 4: Bus operations, BYTE = VIL and Table 5: Bus operations, BYTE = VIH, for details of how to read bit DQ7. The extended block can only be accessed when the device is in extended block mode. For details of how the extended block mode is entered and exited, refer to the Section 4.3.1: Enter Extended Block command and Section 4.3.2: Exit Extended Block command, and to Table 6 and Table 7: Commands, 8-bit mode, BYTE = VIL. C.1 Factory locked extended block In devices where the extended block is factory locked, the security identification number is written to the extended block address space (see Table 28: Extended block address and data) in the factory. The DQ7 bit is set to `1' and the extended block cannot be unprotected. C.2 Customer lockable extended block A device where the extended block is customer lockable is delivered with the DQ7 bit set to `0' and the extended block unprotected. It is up to the customer to program and protect the extended block but care must be taken because the protection of the extended block is not reversible. There are two ways of protecting the extended block: Issue the Enter Extended Block command to place the device in extended block mode, then use the in-system technique with RP either at VIH or at VID (refer to Appendix D, Section D.2: In-system technique and to the corresponding flowcharts, Figure 16 and Figure 17, for a detailed explanation of the technique) Issue the Enter Extended Block command to place the device in extended block mode, then use the programmer technique (refer to Appendix D, Section D.1: Programmer technique and to the corresponding flowcharts, Figure 14 and Figure 15, for a detailed explanation of the technique). Once the extended block is programmed and protected, the Exit Extended Block command must be issued to exit the extended block mode and return the device to read mode. 60/69 M29W064FT, M29W064FB Table 28. Extended block address and data Address x8 000000h-00007Fh 000080h-0000FFh x 16 000000h-00003Fh 000040h-00007Fh Factory locked Extended memory block Data Customer lockable Determined by customer Unavailable Security identification number 61/69 Block protection M29W064FT, M29W064FB Appendix D Block protection Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Appendix A: Block addresses, Table 20 and Table 21 for details of the protection groups. Once protected, program and erase operations within the protected group fail to change the data. There are three techniques that can be used to control block protection, these are the programmer technique, the in-system technique and temporary unprotection. Temporary unprotection is controlled by the reset/block temporary unprotection pin, RP; this is described in the Section 2: Signal descriptions. D.1 Programmer technique The programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. To protect a group of blocks follow the flowchart in Figure 14: Programmer equipment group protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 15: Programmer equipment chip unprotect flowchart. Table 29: Programmer technique bus operations, BYTE = VIH or VIL, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. D.2 In-system technique The in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 16: In-system equipment group protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 17: In-system equipment chip unprotect flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. Note: RP can be either at VIH or at VID when using the in-system technique to protect the extended block. 62/69 M29W064FT, M29W064FB Table 29. Programmer technique bus operations, BYTE = VIH or VIL E G W Address inputs A0-A21 A9 = VID, A12-A21 = block address, others = X A9 = VID, A12 = VIH, A15 = VIH others = X A0, A2, A3 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A21 = block address others = X A0, A2, A3 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A21 = block address others = X Block protection Operation Block (group) protect(1) Chip unprotect Block (group) protection verify Block (group) unprotection verify Data inputs/outputs DQ15A-1, DQ14-DQ0 X X Pass = XX01h Retry = XX00h Retry = XX01h Pass = XX00h VIL VID VID VID VIL pulse VIL pulse VIL VIL VIH VIL VIL VIH 1. Block protection groups are shown in Appendix A, tables 20 and 21. 63/69 Block protection M29W064FT, M29W064FB Figure 14. Programmer equipment group protect flowchart START ADDRESS = GROUP ADDRESS Set-up W = VIH n=0 G, A9 = VID, E = VIL Wait 4s Protect W = VIL Wait 100s W = VIH E, G = VIH, A0, A2, A3 = VIL, A1 =VIH, A6 =VIL, A9 = VID, Others = X E = VIL Wait 4s G = VIL Wait 60ns Read DATA Verify DATA NO = 01h YES A9 = VIH E, G = VIH ++n = 25 YES NO End PASS A9 = VIH E, G = VIH FAIL AI11555 1. Block protection groups are shown in Appendix A, tables 20 and 21. 64/69 M29W064FT, M29W064FB Figure 15. Programmer equipment chip unprotect flowchart START PROTECT ALL GROUPS Block protection Set-up n=0 CURRENT GROUP = 0 A6, A12, A15 = VIH(1) E, G, A9 = VID Wait 4s Unprotect W = VIL Wait 10ms W = VIH E, G = VIH ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1 =VIH, A6 =VIH, A9 = VID, Others = X E = VIL Wait 4s G = VIL INCREMENT CURRENT GROUP Verify Wait 60ns Read DATA NO DATA = 00h YES NO ++n = 1000 YES LAST GROUP YES A9 = VIH E, G = VIH PASS NO End A9 = VIH E, G = VIH FAIL AI11556b 1. Block protection groups are shown in Appendix A, tables 20 and 21. 65/69 Block protection Figure 16. In-system equipment group protect flowchart START Set-up M29W064FT, M29W064FB n=0 RP = VID WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Protect WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Wait 100s WRITE 40h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Verify Wait 4s READ DATA ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH DATA NO = 01h YES RP = VIH End ++n = 25 YES RP = VIH NO ISSUE READ/RESET COMMAND PASS ISSUE READ/RESET COMMAND FAIL AI11563 1. Block protection groups are shown in Appendix A, tables 20 and 21. 2. RP can be either at VIH or at VID when using the in-system technique to protect the extended block. 66/69 M29W064FT, M29W064FB Figure 17. In-system equipment chip unprotect flowchart START PROTECT ALL GROUPS Set-up Block protection n=0 CURRENT GROUP = 0 RP = VID WRITE 60h ANY ADDRESS WITH A0, A2, A3, A6 = VIL, A1 = VIH Unprotect WRITE 60h ANY ADDRESS WITH A0, A2, A3 = VIL, A1, A6 = VIH Wait 10ms WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1, A6 = VIH Verify Wait 4s READ DATA ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1, A6 = VIH INCREMENT CURRENT GROUP NO DATA = 00h YES NO ++n = 1000 YES RP = VIH LAST GROUP YES RP = VIH NO End ISSUE READ/RESET COMMAND ISSUE READ/RESET COMMAND FAIL PASS AI11564 1. Block protection groups are shown in Appendix A, tables 20 and 21. 67/69 Revision history M29W064FT, M29W064FB 10 Revision history Table 30. Date 18-Mar-2008 27-Mar-2008 Document revision history Revision 1 2 Initial release. Applied Numonyx branding. Changes 68/69 M29W064FT, M29W064FB Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved. 69/69 |
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